Design For Security

While a wide variety of techniques exist to enhance design security, many incorporate specialized components and circuitry that add cost and increase complexity.  Adapticom seeks to enhance security by more highly integrating designs, utilizing the most secure and advanced programmable and reconfigurable digital, analog, and mixed signal devices.

Recent advances in device integration have allowed the propagation of reconfigurable devices that encompass a wide variety of common board level functions.  The use of such devices has had a significant positive effect on Design For Security (DFS) efforts.  Rather than adding components and complexity to the design, these components reduce design overhead in a surprising number of ways:

• Reduced component count for simplified BOM.
• Reduced PCB space requirements.
• Increased design revision capability.
• Use of the same devices across multiple products or designs increases purchasing power and simplifies inventory requirements.
• Enhanced design re-use capabilities.
• Simplified R&D through programmable elements.
• Use of similar tools across devices and products reduces engineer educational efforts.

Today's reconfigurable devices have progressed well beyond the FPGA and PAL technologies that proliferated during the 1990's and now include mixed signal devices such as the Motorola 56800E core-based family of Hybrid Controllers, which combine the processing power of a DSP and the functionality of a microcontoller inside a compact 64-pin LQFP.  This device features 60 MIPS performance (at 60 MHz), along with 48 KB of on-chip Flash memory and a comprehensive set of peripehrals.  It extends the capabilities of the 56F8322 by adding additional analog-to-digital converter (ADC) inputs, and timer input/output pins and has the following features:

• On-chip memory includes high-speed volatile and nonvolatile components:
  • 32KB of Program Flash
  • 4 KB of Program RAM
  • 8 KB of Data Flash
  • 8 KB of Data RAM
  • 8 KB of Boot Flash
• Up to 60 MIPS at 60 MHz execution frequency
• DSP and MCU functionality, unified, C-efficient architecture
• JTAG/EOnCE (real-time debugging)
• Four 36-bit accumulators
• 16- and 32-bit bidirectional barrel shifter
• Parallel instruction set with unique addressing modes
• Hardware DO and REP loops
• Three internal address buses
• Four internal data buses
• Architectural support for 8-, 16- and 32-bit single-cycle data fetches
• MCU-style software stack support
• Controller-style addressing modes and instructions
• Single-cycle 16 x 16-bit parallel multiplier-accumulator (MAC)

A second device family of note, the Cypress PSoC CY8C27x, contains over 100 reconfigurable analog and digital library components created from 12 fundamental analog and 8 digital blocks.  Each of these PSoC (Programmable System on Chip) devices contain a 24 MHz 8-bit microcontroller unit (MCU); 16 kbytes of flash memory; 256 bytes of SRAM; an 8x8 multiplier with 32-bit accumulator; power and sleep monitoring circuits; and a precision real-time clock.  The largest device in the family, the CY8C27443 (datasheet), contains the following resources:

• I²C 400KHz Interface
• Internal 24 MHz Main Oscillator
• Three Internal Clock Dividers
• Embedded M8C Microprocessor Core
• 16 KBytes Flash Program Memory (with EEProm emulation)
• 256 Bytes of SRAM
• Memory Protection Features
• 8 Multiplexed Analog Inputs
• 4 Analog Outputs w/ 45 mA drive capability
• 4 direct analog input lines

• Dynamic Reconfiguration
• Counters, Timers and PWMs
• Uarts
• SPI master/slave
• Various A/D, D/A functions
• Filters
  • 2 Pole Filter
  • Low Pass Filter
  • Elliptical Low Pass Filter
  • Band Pass Filter
  • Notch Filter
• Instrumentation Amplifiers

Other configurable devices with analog/digital functions:

• Atmel ATmega169
  16-Kbyte self-programming Flash Program Memory, 1-Kbyte SRAM, 512 Byte EEPROM, 8 Channel 10-bit A/D-converter. JTAG interface for on-chip-debug. 4 X 25 Segment LCD Driver. Up to 16 MIPS throughput at 16 MHz. 5 Volt Operation.
  ( "Butterfly" Development Kit)

• TI MSP430FW427
  The MSP430 family consists of several devices featuring different sets of peripherals targeted for various applications. The devices employ five low power modes and feature a 16-bit RISC CPU, 16-bit registers, digitally controlled oscillator (DCO), allowing wake-up from low-power modes to active mode in < 6µs. The MSP430xW42x series are microcontroller configurations with two built-in 16-bit timers, a comparator, 96 LCD segment drive capability, a scan interface, and 48 I/O pins. (Datasheet)

Other "Design Security" links

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